Bit slicing is a technique for constructing a processor from modules of smaller bit width. Each of these components processes one bit field or "slice" of an operand. The grouped processing components would then have the capability to process the chosen full word-length of a particular software design.
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Bit slice processors usually consist of an arithmetic logic unit (ALU) of 1, 2, 4 or 8 bits and control lines (including carry or overflow signals that are internal to the processor in non-bitsliced designs).
For example, two 4-bit ALUs could be arranged side by side, with control lines between them, to form 8-bit, 16-bit, or 32-bit words (so the designer can add as many slices he wants to make it to manipulate longer word lengths).
A microsequencer or Control ROM would be used to execute logic to provide data and control signals to regulate function of the component ALUs. Examples of bit-slice microprocessor modules can be seen in the Intel 3000 family, the AMD's Am2900 family, the National Semiconductor IMP-16 and IMP-8 family, and the 74181.
Bit slicing (although it was not called that) was also used in computers before integrated circuits. The first bit-sliced machine was EDSAC 2, built at the University of Cambridge Mathematical Laboratory in 1956-8.
Before the era of modern computers (mid-1970s through late 1980s) there was some debate over how much bus width was necessary in a given computer system to make it function. Silicon chip technology and parts were generally much more expensive than today. Using multiple simpler (and cheaper) ALUs was seen as a way to increase computing power in a cost effective manner. 32-bit architectures were being discussed but few were in production.
At the time 16-bit processors were common but expensive, and 8-bit processors, such as the Z80, were widely used in the nascent home computer market.
Combining components to produce bit slice products allowed engineers and students to create more powerful and complex computers at a more reasonable cost, using off-the-shelf components that could be custom-configured. The complexities of creating a new computer architecture were greatly reduced when the details of the ALU were already specified (and debugged).
The main advantage in the late 60's to mid 80's was that bit slicing made it economically possible in smaller processors to use bipolar transistors, which switch much faster than NMOS or CMOS transistors. This allowed for much higher clockrates, for applications where speed was needed; for example DSP functions or matrix transformation, or as in the Xerox Alto, the combination of flexibility and speed, before discrete CPUs were able to deliver that.
In more recent times, the term bitslicing was re-coined by Matthew Kwan [1] to refer to the technique of using a general purpose CPU to implement multiple parallel simple virtual machines using general logic instructions to perform Single Instruction Multiple Data operations. This technique is also known as SWAR, SIMD Within A Register.
This was initially in reference to Eli Biham's 1997 paper A Fast New DES Implementation in Software,[2] which achieved significant gains in performance of DES by using this method.
This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL.